In the integrated circuits or semiconductor devices, transistors and especially metal oxide semiconductor (MOS) transistors, are the most vital element in the applications. However with the continuous narrowing of device size, the submicron scale MOS transistors have to face lots of risky challenges. As the MOS transistors become narrower and thinner, the ability in tolerating the unexpected or non-operational signals becomes a considerable factor. The integrated circuits have to tolerate the non-operational discharge like electrostatic discharge (ESD) without the reliability and the functionality being damaged.
The electrostatic discharge (ESD) attacking has became a serious problem with the down scaling of the feature size of the MOS transistors. A semiconductor device having the power supplies and the input/output pad connections with external sources and circuitry is subject to the problem of ESD. ESD is easily conducted through the input/output and the power lead connections into the internal devices of the integrated circuits and causes the problems like the gate oxide rupture and the overheat damages. The high voltage gradient generated between the contacts and the channels from ESD causes the gate oxide electron injection and the carrier accelerations in the channels. The characteristics and operations of the devices are easily influenced by the inducing effects of ESD. A high level of ESD with several hundred volts to a few thousand volts, which is easily transferred to the pins of an IC package during the handling, can bring a permanent destruction to the internal devices of the IC. For preventing the devices from ESD damaging, the built-in ESD protection circuits are connected between the input/output pads and the internal circuitry. A high level of abnormal discharge conducted into the pins of an IC package is kept out by the ESD protection circuits from flowing into the devices. The discharges are guided through the ESD protection circuits to the substrate or ground and the damage to the semiconductor devices is eliminated.
The SCR (silicon controlled rectifier) device has been well known as one of the most effective ESD protection elements for the input and output pins of the CMOS (complementary MOS) IC's (integrated circuits). The SCR device has a great bypassing current at latch-up state and thus makes it the most efficient device in protecting ESD with limited area. The drawback of high triggering voltage of conventional SCR device had been eliminated with the LVTSCR (low-voltage triggering SCR) devices. The trigger voltage of LVTSCR in the submicron CMOS technology had been lowered to be about ten volts. The following works can be referenced.
1! A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," Proc. Symp. On VLSI Tech., 1990, pp. 75-76.
2! M. -D. Ker, C. -Y. Wu, and H. -H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, pp. 588-598, 1996.
3! M. -D. Ker, H. -H. Chang and C. Y. Wu, "ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure," Technical Digest of IEDM, 1995, pp. 543-546.
Referring to FIG. 1a, the device structure of a LVTSCR 10 is illustrated. The LVTSCR 10 has an anode 10a, a control gate 10b, and a cathode 10c. As an example, the anode 10a connects to a pad and the control gate 10b and the cathode 10c connect commonly to ground for ESD protection. The I-V characteristics of the LVTSCR 10 are shown in FIG. 1b. The LVTSCR 10 can sustain high ESD voltage with only occupying a much smaller layout area than conventional ESD protection circuits by it's low holding voltage. To avoid the unexpected ESD damages on the internal circuits beyond the input or output ESD protection circuits, an effective ESD clamp circuit has to be placed between the VDD and VSS power lines of an IC to provide the whole-chip ESD protection. The following references discuss the ESD damages and the ESD clamp circuit.
4! C. Duvvury, R. N. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. On Electron Devices, pp. 2133-2139, 1988.
5! C. Johnson, et al., "Two unusual HBM ESD failure mechanisms on a mature CMOS process," Proc. EOS/ESD Symp., 1993, pp. 225-231.
6! H. Terletzki, et al., "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress," IEEE Trans. Electron Devices, pp. 2081-2083, 1993.
7! M. Chaine, S. Smith, and A. Bui, "Unique ESD failure mechanisms during negative to Vcc HBM tests," Proc. EOS/ESD Symp., 1997, pp. 346-355.
8! R. Merrill and E. Issaq, "ESD design methodology," Proc. EOS/ESD Symp., 1993, pp. 233-237.
9! E. Worley, et al., "Sub-micron chip ESD protection schemes which avoid avalanching junctions," Proc. EOS/ESD Symp., 1995, pp. 13-20.
10! M. -D. Ker and S. -C. Liu, "Whole-chip ESD protection design for submicron CMOS VLSI," Proc. IEEE ISCAS, 1997, pp. 1920-1923.
Thus the area-efficient lateral SCR devices had been used in the VDD-to-VSS clamp circuits to effectively bypass the ESD current away from the internal circuits. The following works can be referenced.
11! G. D. Corft, "ESD protection using a variable voltage supply clamp," Proc. EOS/ESD Symp., 1994, pp. 135-140.
12! J. T. Watt and A. J. Walker, "A hot-carrier triggered SCR for smart power bus ESD protection," Tech. Digest of IEDM, 1995, pp.341-344.
The LVTSCR in the ESD protection circuit is easily triggered on by the external noise pulses with the low trigger voltage and current. Thus the LVTSCR can be easily triggered on even at normal operation conditions. Since the holding voltage of the LVTSCR is only around one volt, the LVTSCR might be triggered on by the external pulses and latched the input or output signals. The input or output signals can be destroyed and kept from reaching the operational devices of the internal circuit. Referring to FIG. 2a, a schematic diagram illustrating the noise pulse Z1 at an input pad 12 to trigger on the LVTSCR 10 is shown. FIG. 2b illustrates a schematic diagram showing the noise pulse Z2 at an output pad 16 to trigger on the LVTSCR 10. The normal input/output signals are thus latched by the LVTSCR 10 to cause the failure or the malfunction in the system applications.
In the test of authorizing the "CE" mark from the European Community, an ESD gun with the ESD voltage of 8 KV to 15 KV is used to test the electromagnetic compatibility (EMC) of the electronic products. The related references are as follows.
13! Electromagnetic compatibility for industrial-process measurement and control equipment, International Standard IEC 801-2, 1991.
14! J. Maas and D. Skjeie, "Testing electronic products for susceptibility to electrostatic discharge," Proc. of EOS/ESD Symp., 1990, pp. 92-96.
15! W. T. Rhoades, "ESD stress on IC's in equipment," Proc. EOS/ESD Symp., 1990, pp. 82-91.
During the system-level ESD/EMC testing, the power lines of the IC's in the system board can be coupled with an overstress voltage even up to several hundreds volts. The system-level ESD/EMC test is illustrated in FIG. 3a. The typical ESD-coupled transient voltage on the VDD pin of an IC in the system board is illustrated in FIG. 3b. Such a system-level ESD/EMC event easily causes the transient-induced latchup failure in the CMOS IC's. The topics are discussed in the following references.
16! E. Chwastek, "A new method for assessing the susceptibility of CMOS integrated circuits to latch-up: the system-transient technique," Proc. EOS/ESD Symp., 1989, pp. 149-155.
17! G. Weiss and D. Young, "Transient-induced latchup testing of CMOS integrated circuits," Proc. EOS/ESD Symp., 1995, pp. 194-198.
If the lateral SCR or the LVTSCR are used as the ESD clamp devices between the VDD and VSS power lines of an IC 11!-12!, such ESD-protection SCR devices are easily triggered on by the system-level ESD/EMC transient pulses to cause very serious latchup problem in the CMOS IC's.
Although the LVTSCR can provide very effective ESD-protection capability within a much small layout area, the LVTSCR still can not be safely used in the input and output ESD protection circuits or the VDD-to-VSS ESD clamp circuits. The latchup problem in destroying operational signals from the low holding voltage of the conventional LVTSCR devices must be solved. The ESD protection of the integrated circuits fulfilling future specification of small area and high bypassing current is in highly demand.